Retrochallenge 2017/10

geoRAMThis year our staff decided to enter the retrochallenge competition. Our goal is to reverse engineer the Berkely softworks geoRAM and publish what we discover under the GPL. The geoRAM is a 512KB memory expansion for the Commodore 64 and 128. Unlike the Commodore 1750 REU, which contain a custom chip, the geoRAM is built completely out of standard TTL chips.

The geoRAM is a banked system. The registers at $dfff and $dffe select which 256 bytes page is visible in the $de00-$deff range. The $dfff register selects a 16KB block out of the total memory, the register at $dffe selects the actual 256 bytes page within the selected block. Valid values for a standard geoRAM are 0-31 for the Block register and 0-63 for the page register. It is possible to extend the block register to 8-bit to create a 4MB geoRAM.

Teardown

The picture below shows the full PCB without the plastic shell. It is easy to see the DRAM section with four 44C256 (256Kx4) memories. It is also easy to see the two 74HC378 6-bit registers that control the geoRAM paging scheme.

geoRAM

The full list of ICs used in the design is in the following table.

Refdes Part Numebr Description Notes
U1 74HC10 Triple 3-input NAND Gate State machine logic
U2 74HC194 4-bit Bidirectional Shift Register State machine for DRAM access and refresh
U3 74HC74 Dual D Flip−Flop with Set and Reset State machine reset and register write enable
U4, U5 74HC378 Hex D-Type Flip-Flop with Clock Enable Paging registers
U6, U7, U8 74HC157 Quad 2-input Multiplexer Multiplex Rows and Columns
U9, U10, U11, U12 44C256 256 x 4 Bit CMOS Dynamic RAM with Fast Page Mode 512KB total
U13 74HC139 Dual 2-to-4 Line Decoder/Demultiplexer Select for DRAM and registers

Like most of the PCBs of the time the board is just 2-layers making reverse engineering quite easy. Simple visual inspection and an ohmmeter are sufficient to fully trace every single net in the design.

Schematics Description

The schematics can be partitioned in a few main blocks. The register section is formed by U3B, U4, U5 and U13A. The decoder U13A select the correct register based on IO/2 (the system asserts this when the address is within $df00-$dfff), A0 and A7. Because of the incomplete decoding the two registers are mirrored in the range $df80-$dfff. U3B produces a clean clock for U4 and U5, if the enable is asserted a write to the register will occur. U4 maps to $dfff (block register) and U5 maps to $dffe (page register).

The memory section includes U6-8, U9-U12 and U13B. DRAMs require the address to be split into Row and Column which are multiplexed on the same pins. The three 74HC157 multiplexers (U6-U8) serve exactly this purpose. The U13B decoder selects the DRAM array if the I/O1 signal is asserted ($de00-$deff) and generates the output enable (OEx) or write enable (WEx) to the correct set of DRAMs. U10 and U12 map to the first 256KB of expanded memory while U9 and U11 map to the second 256KB section.

Filed under: