Both the commodore 64 and the 128 have a software UART implementation that limits the useful speed to 2400 bauds. To work around this limitation Dr. Evil Labs and later CMD produced the SwiftLink232 and Turbo232 cartridges based on the 6551 ACIA chip. Both of these have been out of production for a very long time. GLINK232T is a modern replacement for the CMD Turbo232 allowing the commodore 64/128 to communicate at speeds up to 230400 bauds.
Similarly to the Turbo232 and the Swiftlink, the card can be configured using jumpers at either the $DE00 or $DF00 I/O address and can use either the NMI or IRQ interrupt line (most native software use NMI, but CP/M uses IRQ).
The Turbo232 cartridge is backwards compatible with the Swiftlink. The card uses a 3.6864MHz oscillator (double the standard for a 6551) to match the baud rate table of the Swiftlink. The additional baud rates (203400, 115200 and 57600) are obtained by bypassing the 6551 baud rate generator and optionally dividing the oscillator output by 2 or 4.
|$Dx00||Data||6551 register (same as Swiftlink)|
|$Dx01||Status||6551 register (same as Swiftlink)|
|$Dx02||Command||6551 register (same as Swiftlink)|
|$Dx03||Control||6551 register (same as Swiftlink), writing $x0 enables the ES register|
|$Dx07||ES||See description below for bit field|
The Enhanced Speed (ES) register implements only bits 0-2. Bits 3-7 are unimplemented.
Bit 2 is read only. Its value will be 1 when the Control register lower 4 bits are all zero to signal the card is in ES mode and the higher baud rates are active. A value of 0 signals the standard Swiftlink baud rates.
Bits 0 and 1 select the enhanced speed baud rate. 00 selects 230400 baud, 01 selects 115200, and 10 selects 57600. 11 is undefined.
The GLINK232T schematics is almost identical to the earlier GLINK232T-C00. The only difference is one additional footprint for the crystal oscillator. The 6551 ACIA (U1) is used to keep compatibility with the SwftLink and the Turbo232. MAX232 level translators (U4 and U5) are used to provide true RS-232 signal levels. The address decoder and the delayed phi2 clock required to meet the ACIA timing specifications have been integrated into the U3 16V8 PAL. The ES register is implemented into the second 16V8 PAL (U2).
The board can be configured as a swiftlink only by the following BOM options.
|R4||0 ohm||no stuff|
|R5||0 ohm||no stuff|
|R6||0 ohm||no stuff|
|R7||no stuff||0 ohm|
Speeds above 38400 are a challenge for the 8-bit commodores. At 115200 baud a 1-MHz 6502 has less than 90 clock cycles between input bytes. In these conditions is very difficult to perform any operation beside just receiving data.
Only specific hw/sw configurations work reliably when simultaneously displaying the output.
|C64||Novaterm 9.6c (Soft 80)||38400|
|C64||GTERM 0.18 (Soft 80)||115200|
|C128||DesTerm 3.02 (80-col)||115200|