The apple IIgs is the most advanced computer in the Apple II series. Equipped with a 65c816 8/16-bit CPU with 24-bit address space it could address up to 16MB of memory. The original rom 01 model shipped with 256KB of fast RAM, the revised rom 3 shipped with 1MB (both had an additional 128KB of standard RAM and 64KB of sound RAM). RAMGS/4 is a newly designed 4MB memory expansion card for this great classic computer.
This design is a further improvement over the previous SIMM based RAMGS/4.
Sourcing 30-pin SIMM sockets has been increasingly difficult so the design has been changed to a full SMD design with TSOP memories and a single 16V8 PLD.
The data bus is directly connected to the DRAM chips, the address bus FRA0-FRA9 is connected though series termination directly to the corresponding DRAM pins (note the signal swaps to simplify the routing).
U1 combines CROW0 and CROW1 to generate the appropriate FRA10 and FRA11. U1 also generates the modified WE# signal required to support 16Mbit chips (see section at the end of the article for a detailed explanation).
Address Drive Strength
Most vintage expansion cards buffer the address to the drams on the card. After extensive probing on our previous cards it turns out that the buffers are unnecessary on the RAMGS/4 because of the limited loading (max of 3 devices) and very short traces (less than 50mm). For comparisons the apple 1MB expansion card has 32 loads and traces exceeding 300mm. Actually the FPI I/O drive is already too strong for the RAMGS/4 layout given the negative overshoot exceeds 2V in the scope captures.
Adding series termination on the address lines reduces the overshoot at the expense of slower rise and fall time. The following two images show the effect of 56ohm and 100ohm series termination.
The Apple IIgs seems to perform only standard read cycles, early write cycles and CAS before RAS refresh cycles. We have not seen any fast page mode nor read-modify-write cycles.
Upon close inspection of the memory datasheets is clear that the CAS before RAS refresh cycle is different between the 1Mbit and the 4Mbit parts. In particular, the 4Mbit devices require WE to be high at the falling edge of RAS (WE is a don't care in the 1Mbit devices). Issuing a RAS before CAS refresh cycle with WE low on the 4Mbit DRAM enables the device test mode.
The IIgs follows the 1Mbit specification and the state of WE during a refresh cycle is undetermined (it is actually the state left by the transaction right before the refresh cycle). This behavior randomly enables the test mode in the memories with catastrophic results to the running programs.
The logic in the PLD detects when a refresh cycle is in progress and forces the de-assertion of WE# when necessary.