A new version of this project is available here
The design uses the same DRAMs and shares most of the basic design with our regular RAMGS. Besides the obvious increase in number of DRAMs the only difference is the bank selection and refresh circuit formed by U4B, U8 and U9. The flip-flop U4B latches bit 6 of the bank address (this selects the low or high 4MB of expansion memory). U8A and U8B make sure that refresh cycles are broadcasted to both banks regardless of the state of the flip flop. The rest of U8 and U9 just generate the RAS and CAS signals for the two memory banks.
Due to the limitation of the IIgs core logic the card is not 100% DMA compatible.